DV - Staff Verification Engineer - Serdes
EliyanChiplet Interconnects company
Bay AreaLead
Intel Capital
Tiger Global Management
Seligman Ventures
Cisco Investments
Lumentum
Micron
Software Engineering
About the role
TL;DR
Lead verification of Serdes in a fast-paced chiplet startup.
- •Join the leading chiplet startup! As an Eliyan Staff Design Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow's chiplet-based systems.
- •Key Responsibilities Develop and execute verification plans for Serdes, other PHYs, DSP blocks, TX/RX equalization and CDR.
- •Create and maintain SystemVerilog/UVM-based verification environments Write and debug SystemVerilog/UVM compliant test cases for block and chip level Maintain regression environments Collaborate with design team to ensure design quality Requirements BS + 7 years of verification experience with 4+ years in PHY or high-speed interfaces Deep verification expertise in SerDes/PCIePHY, TX/RX equalization, CDR Strong expertise in UVM/SystemVerilog, test environment and assertion coding Experience in verifying mixed signal IPs as well as integration of VIPs
Required skills
PythonTechnical LeadershipMentoring
Benefits & perks
ONSITE M-F
Tech stack
PythonPerl
