Digital Design Verification Engineer
OLIXAI Hardware company
Bristol, United KingdomSenior
Plural
LocalGlobe
Hummingbird Ventures
Entrepreneurs First
Transition
Crane Venture Partners
About the role
TL;DR
Take ownership of the functional correctness of high-speed, real-time data-processing silicon.
- •We are seeking highly skilled and motivated Senior / Staff Digital Verification Engineers with a strong background in CMOS digital design and verification to take ownership of the functional correctness of high-speed, real-time data-processing silicon, from early algorithm modelling through verified RTL, sign-off, and silicon bring-up.
- •Key Responsibilities Own end-to-end verification of high-throughput digital pipelines supporting multi-GSPS input rates, continuous streaming data paths, deep pipelining, and robust hand-shaking in advanced CMOS nodes Develop and maintain comprehensive verification environments using SystemVerilog/UVM, including constrained-random testing, coverage closure, and regression automation Define and implement assertion-based verification strategies for control logic, data-path correctness, CDC/RDC, and protocol compliance Apply formal verification techniques (property checking, assertions, equivalence checking) to complement simulation-based verification and accelerate bug discovery Collaborate closely with digital design, optical-hardware, mixed-signal, and software teams to ensure correct integration across clock domains, interfaces, and firmware abstractions Requirements 5+ years of hands-on experience in digital verification for high-performance ASICs or SoCs Ownership of verification for at least one complex block or subsystem processing continuous real-time data streams Strong proficiency in SystemVerilog, assertions (SVA), and modern verification methodologies (e.g.
- •CocoTB) Proven experience verifying designs operating in GHz-class clock domains, including CDC/RDC analysis Familiarity with industry-standard EDA flows: RTL simulation, formal verification, linting, CDC/RDC, STA, power-intent (UPF/CPF), and gate-level simulation
Nice-to-have skills
Python
Benefits & perks
Competitive Salary, Equity & Ownership, Proximity Bonus, Retirement Benefits
Tech stack
Python