TL;DR
Lead DFT architecture for AI accelerator SoC, from strategy to production.
- •Lead the end-to-end DFT architecture for a large multi-core AI accelerator SoC, from strategy through silicon bring-up and production, ensuring scalable, power-aware, high-coverage test solutions.
- •Key Responsibilities Define and own DFT architecture (scan, compression, MBIST, LBIST, boundary scan) Set DFT strategy, methodology, flow and signoff criteria and integrate tools into EDA flows Define hierarchical DFT for multi-core designs and large memory systems Work with RTL, physical design, test and product teams for silicon bring-up and yield ramp Requirements Strong DFT experience for complex ASIC/SoC designs (typically 10+ years) Ownership of DFT architecture on at least one large tapeout Deep expertise in scan, compression, ATPG and MBIST and experience with Synopsys or Tessent Understanding of clocking, resets, power domains, physical constraints and silicon debug
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