Principal DFT Engineer
FortellAI-powered Hearing company
San Francisco, United States$160,000 – $300,000Lead
Founders Fund
Thrive Capital
Valor Equity Partners
Sequoia Capital
Khosla Ventures
K5 Global
New
About the role
TL;DR
Lead full-chip test architecture for AI-powered hearing technology.
- •Fortell is seeking an experienced Principal DFT Engineer to lead full-chip test architecture, from scan and compression logic to MBIST and silicon debug.
- •You will collaborate across teams to deliver production-ready silicon with world-class test coverage and diagnostic capability.
- •Key Responsibilities Develop, architect and implement comprehensive DFT structures tailored to specific design requirements.
- •Design and implement robust DFT infrastructure, including scan chains, compression logic, MBIST, BIST, JTAG.
- •Generate high-quality ATPG test vectors for logic and memory, and analyze DFT coverage.
- •Perform MBIST verification including simulation of memory test algorithms, fault modeling, and debug of failing patterns.
- •Collaborate closely with STA, physical design, power, and memory compiler teams to debug and resolve DFT/MBIST-related challenges.
- •Requirements Strong understanding of industry standards and best practices in DFT, ATPG, JTAG, and MBIST.
- •Proven experience in developing DFT specifications and architectures for complex designs.
- •Expertise in debugging DFT issues, including ATPG patterns, MBIST implementations, coverage analysis.
- •Proficiency in Cadence tools like Modus and Genus for DFT implementation, vector generation, and verification.
- •Efficient scripting skills using TCL for automating tasks and developing custom flows.
Domain expertise
deeptechhealthcare
Benefits & perks
stock options, generous benefits package
Tech stack
PythonBash