Lead end-to-end physical implementation of advanced ASIC/SoC designs.
•Fractile seeks a Senior/Principal Physical Design Engineer to lead end-to-end physical implementation of advanced ASIC/SoC designs, optimising performance, power, and area while ensuring manufacturability.
•Key Responsibilities Drive floorplanning, placement, CTS, routing, and sign-off for complex chips.
•Perform synthesis, STA, timing closure and PPA optimization.
•Plan and analyse power (IR drop, EM) and low-power techniques.
•Ensure DRC/LVS and physical verification sign-off; interface with foundries.
•Develop and automate EDA flows and collaborate with RTL, DFT, and architecture teams.
•Requirements 7+ years in physical design at advanced nodes (7nm/5nm or below).
•Proficiency with place & route, STA, and sign-off EDA tools.
•Strong CMOS/process understanding and manufacturability experience.
•Scripting skills (TCL, Perl, Python) for automation.
•Experience with low-power design and timing/IR analysis.