Senior Verification Engineer I

Senior Verification Engineer I for FPGA and digital design verification in aerospace.

• •CesiumAstro is seeking a Senior Verification Engineer I to contribute to the development of cutting-edge phased arrays for satellites and aerospace systems.
• •This role involves working in a dynamic startup environment with a focus on FPGA and digital design verification.
• •Key Responsibilities Evaluate and implement FPGA and digital design simulation, verification, and emulation infrastructure.
• •Develop and maintain continuous integration and regression testing infrastructure.
• •Create UVMf-based testbenches using System Verilog and integrate with MATLAB and Python models.
• •Lead the development of reusable custom VIP modules and mentor junior engineers.
• •Requirements BS/MS degree in Computer Science, Electrical Engineering, or Computer Engineering.
• •Minimum of 4 years of industry experience in verification and automation.
• •Deep knowledge of FPGA digital design verification techniques (VHDL, Verilog, SystemVerilog, C/C++, SystemC, UVM/UVMf, DPI-C, TLM, Formal CDC, QEMU, VIP).
• •Expert-level knowledge of digital design automation infrastructure (CI, regression testing, HIL testing).